Effect of MOSFET gate-to-drain parasitic capacitance on class-E power amplifier
Xiuqin Wei, Hiroo Sekiya, Shingo Kuroiwa, Tadashi Suetsugu, and Marian K. Kazimierczuk
2010 IEEE International Symposium on Circuits and Systems (ISCAS2010) , pp.3200-3203 , June, 2010. [pdf document]

<Abstract>

In this paper, we present analytical expressions for the waveforms and design equations for achieving the ZVS/ZDS conditions in the class-E power amplifier, taking into account the gate-to-drain parasitic capacitance of the MOSFET. We also give a design example along with PSpice simulation and experimental results. The voltage waveforms obtained from both the PSpice simulation and the circuit experiment achieved the class-E ZVS/ZDS conditions completely, which verify the analytical expressions. The results in this paper indicate that it is important to consider the effect of the MOSFET gate-to-drain capacitance for achieving the class E ZVS/ZDS conditions. The experimental power conversion efficiency achieved 92.8 % at output power Po = 4.06 W and operating frequency f = 7 MHz.