Design of class-E amplifier with MOSFET linear gate-to-drain and nonlinear drain-to-source capacitances
Xiuqin Wei, Hiroo Sekiya, Shingo Kuroiwa, Tadashi Suetsugu, and Marian K. Kazimierczuk
IEEE Transactions on Circuits and Systems Part I: Regular Papers, vol.58, no.10, pp.2556-2565, Oct., 2011. [pdf document]

<Abstract>

This paper presents expressions for the waveforms and design equations to satisfy the ZVS/ZDS conditions in the class-E power amplifier, taking into account the MOSFET gate-to-drain linear parasitic capacitance and the drain-to-source nonlinear parasitic capacitance. Expressions are given for power output capability and power conversion efficiency. Design examples are presented along with the PSpice-simulation and experimental waveforms at 2.3 W output power and 4 MHz operating frequency. It is shown from the expressions that the slope of the voltage across the MOSFET gate-to-drain parasitic capacitance during the switch-off state affects the switch-voltage waveform. Therefore, it is necessary to consider the MOSFET gate-to-drain capacitance for achieving the class-E ZVS/ZDS conditions. As a result, the power output capability and the power conversion efficiency are also affected by the MOSFET gate-to-drain capacitance. The waveforms obtained from PSpice simulations and circuit experiments showed the quantitative agreements with the theoretical predictions, which verify the expressions given in this paper.