Pipelined successive interference cancellation with parallel processing for a DS/CDMA system <Abstract> Since Direct Sequence/Code Division Multiple Access systems suffer from Multiple Access Interference, Interference Cancellation (IC) scheme should be used. There are two major IC schemes. One is the Successive Interference Cancellation (SIC) scheme and the other is the Parallel Interference Cancellation (PIC) scheme. The Bit Error Rate (BER) performance of the SIC scheme outperforms the PIC scheme under fading channel but faces the problem of large processing delay. The Pipelined Successive Interference Cancellation (PSIC) scheme is a pipelined modification of the SIC to compensate the large processing delay of the SIC. However, processing delay of the PSIC scheme increases as the number of users increases. Therefore, it is a problem that the processing delay of the PSIC scheme is larger than the PIC scheme. Moreover, the BER performance is inferior to multi stage SIC. In this paper, we propose the PSIC with parallel processing. In the proposed scheme, the users are ranked in decreasing order of their respective received signal power using the power ranking information extracted from the power ranking scheme. Then the proposed scheme divides all users into some groups. The parallel processing is applied to the users within a same group. The pipelined processing is performed among the groups. The simulation results show that the BER performance of the proposed scheme outperforms than the PSIC scheme in spite of less than half the processing delay. |