Design of load-independent class-E inverter with MOSFET parasitic capacitances
Weisen Luo, Xiuqin Wei, Hiroo Sekiya, and Tadashi Suetsugu
62nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2019)), Dallas, TX, USA, Aug., 2019. [pdf document]

<Abstract>

This paper presents a numerical design method of the load-independent class-E inverter with MOSFET parasitic capacitances. A design example is shown along with its LTspice simulation and laboratory experiment. There are no changes in the output-voltage waveforms and all the switch-voltage waveforms satisfy the zero-voltage-switching(ZVS) condition even the load-resistance value is shifted from the desired one. Additionally, the results obtained from the LTspice simulation and laboratory experimental show quantitative agreement with the numerical predictions, which has shown the accuracy of the proposed design approach given in this paper and validated the effectiveness of the load-independent class-E inverter with MOSFET parasitic capacitances.